A wide band receiver such as a frequency spectrum analyzer is used to analyze frequency components of an incoming signal. An example of conventional spectrum analyzer utilizes a local oscillator whose frequency is digitally controlled by a step sweep signal through a direct digital synthesizer (DDS) technology. Such a conventional example of spectrum analyzer is explained with reference to FIGS. 4, 5 and 6.
In the example of FIG. 4, the frequency spectrum analyzer is formed of a frequency converter 50, a detector 62, a display arithmetic unit 64, and a display 68. As also shown in FIG. 4, the frequency converter 50 includes an attenuator 51, a first frequency mixer 52, a local oscillator 30, a second frequency mixer 53, a fixed local oscillator 54 and a band pass filter (BPF) 55.
The frequency converter 50 receives an input signal 100 to be analyzed and converts the input signal to an intermediate frequency signal when the local oscillator sweeps its frequency for a specified frequency range. In this example, the intermediate frequency signal is created by mixing the input signal 100 with a first local signal from the local oscillator 30 and a second local signal from the fixed local oscillator 54. The intermediate frequency signal is filtered by the BPF 55 to a predetermined band width and is then provided to the detector 62.
The BPF 55 may be formed of a plurality of band pass filters having a variety of resolution bandwidth which are set by a user. When two or more frequency spectrum in the input signal have small frequency differences, a band pass filter of sufficiently small bandwidth must be used to fully distinguish the frequency spectrum from the others.
The detector 62 detects DC voltages, i.e., envelope voltages, of the intermediate frequency signals from the BPF 55. The detected voltages are provided to the display 68 through the display arithmetic unit 64. The frequency spectrum contained in the input signal are displayed on the display 68 in a frequency domain wherein the horizontal axis is a frequency having a variable frequency span (frequency range on a full display) and the vertical axis is a power level.
The local oscillator 30 is a sweep oscillator which can sweep a desired frequency range in a step manner with use of the DDS (direct digital synthesizer) technology. As shown in FIG. 5, the local oscillator 30 includes a DDS time base 32, a DDS 40, a D/A (digital to analog) converter 34, a LPF (low pass filter) 35, a phase comparator 36, a divider 37, an integrator 38, and a YTO (YIG-tuned oscillator) 39. A phase lock loop (PLL) is formed of the YTO 39, the divider 37, the phase comparator 36, and the integrator 38.
The DDS time base 32 receives a reference clock 31 and sweep conditions 33 which includes a span (sweep frequency range) and a sweep time T.sub.swp and delivers a clock signal 32.sub.ck to the DDS 40. The clock signal 32.sub.ck has a unit step time T.sub.step which is produced by dividing the reference clock 32 by a division factor Div, i.e., T.sub.step =(reference clock 31)/Div. Thus, one clock time period of the clock signal 32.sub.ck is equal to the unit step time T.sub.step in the step sweep of the local oscillator 30.
The DDS 40 is a synthesizer which generates digital data representing a digital sine wave of a desired frequency. As shown in FIG. 6, the DDS 40 is formed of a frequency register 42, an adder 44, and a ROM table memory 46.
The frequency register 42 stores advance phase data 42.sub.dt and provides the phase data 42.sub.dt to one input of the adder 44. The advance phase data is 32 bit data, for example, and defines a magnitude of phase advance of a sine wave to be generated by the local oscillator 30. By this data, as shown in a stepped ramp signal of FIG. 7A, a unit step frequency 92 is accumulated at every unit step time T.sub.step, which results in one sweep time T.sub.swp =M.times.T.sub.step. Here, M is a constant number of steps, such as 2,048 steps, in an overall sweep.
The adder 44 is for example a 32 bit accumulator to advance the unit phase of the above noted unit frequency 92 of the sine wave. At every clock signal 32.sub.ck from the DDS time base 32, one input terminal of the adder 44 receives the advance phase data 42.sub.dt from the register 42, while the other input terminal receives the data from a register 44.sub.r connected to the output of the adder 44. The register 44.sub.r holds the output data of the adder 44 produced in the previous accumulation cycle. Thus, the adder 44 accumulates the data at the two input terminals and the result is latched in the register 44.sub.r for the next cycle.
The ROM table memory 46 converts the received data to step like sine wave data. For example, the ROM table memory 46 uses data in the upper 10 bit of 32 bit data from the adder 44 as address data to read 10 bit sine wave data 46.sub.dt from the table memory 46. The sine wave data 46.sub.dt is supplied to the D/A converter 34 shown in FIG. 5.
The D/A converter 34 in FIG. 5 converts the 10 bit sine wave data 46.sub.dt to a step like analog signal. The LPF 35 removes frequency components of the clock signal 32.sub.ck in the step like analog signal to make a sine wave analog signal and provides the sine wave analog signal to one input terminal of the phase comparator 36.
The phase comparator 36 detects phase differences between the two input signals and generates voltage signals representing the phase differences. Namely, the phase comparator 36 receives a reference phase signal from the DDS through the LPF 35 as well as an oscillation signal 39.sub.osc of the YTO 39 whose frequency is divided by 1/N at the divider 37. The YTO 39 is a voltage controlled oscillator. The phase comparator 36 compares the phases of the two input signals and generates a voltage signal representing the phase differences between the two input signals. The voltage signal is applied to the integrator 38 which is typically a low pass filter. The integrator 38 integrates the voltage signals to produce an analog DC voltage which is supplied to an voltage control input of the YTO 39.
The YTO 39 is a variable resonance oscillator in a microwave frequency band using, for example, a YIG (Yttrium Iron Garnet) crystal. The YTO 39 receives the analog DC voltage from the integrator 38 and generates the step sweep frequency signal 39.sub.osc which is phase locked by the PLL loop noted above. The sweep signal 39.sub.osc is supplied to the frequency mixer 52 in the frequency converter 50 to convert the frequency of the input signal 100 to the intermediate frequency signal through the first and second frequency mixers 52 and 53.
As in the foregoing, the sweep operation of the local oscillator 30 is performed in the step manner. Therefore, as shown in FIG. 7A, the frequency of the local signal is also swept in the step like manner, and thus, the swept frequency varies discontinuously. As a result, a dynamic spurious response which is inverse proportional to the unit step time T.sub.step, i.e., .DELTA.f=1/T.sub.step is induced as shown in FIG. 7B. Because the spurious frequency .DELTA.f is close to a center frequency f.sub.o of the input signal under measurement, it is difficult to remove this dynamic spurious by a filter circuit. Thus, the spurious will be displayed at the frequency positions f.sub.o.+-..DELTA.f on the display of the frequency spectrum analyzer even though the input signal does not have the frequency spectrum .DELTA.f.